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Papers

1. ``A drive of input and output impedance effects of functional blocks into a frequency shift of active circuits,'' Kazuyuki Wada, Nobuo Fujii, and Shigetaka Takagi, IEICE Trans. Fundamentals, Vol. E78-A, No. 2, pp. 177-184, Feb. 1995.
2. ``Topology-Independent Predistortion for Integrator-Based Filters,'' Kazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, and Nobuo Fujii, IEICE Trans. Fundamentals, Vol. E79-A, No. 2, pp. 176-183, Feb. 1996.
3. ``Automatic Tuning System for Integrator-Based Continuous-Time Filters,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Analog Integrated Circuits and Signal Processing, Vol 16, No. 3, pp. 225-238, Aug. 1998.
4. ``Reduction in Characteristic Deviations due to Parasitic Elements on Continuous-Time Filters Using Integrators,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, IEICE Trans. Fundamentals (Japanese Edition), Vol. J81-A, No. 7, pp. 1049-1058, July 1998.
5. ``Improvement on Frequency Characteristics of Integrator-Based Filters by Reducing Spread of Unity-Gain Frequencies,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, IEICE Trans. Fundamentals (Japanese Edition), Vol. J81-A, No. 9, pp. 1205-1212, Sep. 1998.
6. ``A Novel Design Strategy for Class A CMOS Second Generation Current Conveyors,'' Sohrab Emami, Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, IEICE Trans. Fundamentals, Vol. E84-A, No. 2, pp. 552-558, Feb. 2001.
7. ``Wide-Input Range Linear Voltage-to-Current Converter Using Equivalent MOSFETs without Cutoff Region,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, IEICE Trans. Fundamentals, Vol. E85-A, No. 2, pp. 347-353, Feb. 2002.
8. ``Fully On-Chip Active Guard Band Circuit for Digital Noise Cancellation,'' Shigetaka Takagi, Retdian Agung Nicodimus, Kazuyuki Wada, and Nobuo Fujii, IEICE Trans. Fundamentals, Vol. E85-A, No. 2, pp. 373-380, Feb. 2002.
9. ``Extension of Current Conveyor Concept and Its Applications,'' Takahide Sato, Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, IEICE Trans. Fundamentals, Vol. E85-A, No. 2, pp. 403-413, Feb. 2002.
10. ``Reduction of Effect due to Parasitics in Integrated Wave Filters,'' Mitsuya Otake, Kazuyuki Wada, Yoshiaki Tadokoro, Trans. of IEEJ Soc. C, Vol. 124, No. 9, pp. 1797-1804, Sep. 2004.
11. ``Active Shield Circuit for Digital Noise Suppression in Mixed-Signal Integrate Circuits,'' Retdian Agung Nicodimus, Shigetaka Takagi, and Kazuyuki Wada, IEICE Trans. Fundamentals, Vol. E88-A, No. 2, pp. 438-443, Feb. 2005.
12. ``Design Optimization of Active Shield Circuits for Digital Noise Suppression Based on Average Noise Evaluation,'' Retdian Agung Nicodimus, Hiroto Suzuki, Kazuyuki Wada, and Shigetaka Takagi, IEICE Trans. Fundamentals, Vol. E88-A, No. 2, pp. 444-450, Feb. 2005.
13. ``Equivalent Linear Floating-Resistor Pair in Balanced MOS Analog Circuits and Its Applications,'' Kazumasa Ito, Kazuyuki Wada, Hiroto Suzuki, and Yoshiaki Tadokoro, IEICE Trans. Electronics, Vol. J88-C, No. 12, pp. 1198-1207, Dec. 2005. (In Japanese)
14. ``Approximate Design of RC Polyphase Filters with Amplitude Characteristics Being Flat in Passbands and Equiripple in Stopbands,'' Kazuyuki Wada and Yoshiaki Tadokoro, IEICE Trans. Fundamentals, Vol. J88-A, No. 12, pp. 1478-1486, Dec. 2005. (In Japanese)
15. ``Synthesis Method of All Low-Voltage CMOS Instantaneous-Companding Log Domain Integrators,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, IEICE Trans. Fundamentals, Vol. E90-A, No. 2, pp. 339-350, Feb. 2007.
16. ``Band Connections for Digital Substrate Noise Reduction using Active Cancellation Circuits,'' Hiroto Suzuki, Kazuyuki Wada, and Yoshiaki Tadokoro, IEICE Trans. Fundamentals, Vol. E90-A, No. 2, pp. 372-379, Feb. 2007.
17. ``A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-ƒÊm CMOS,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, IEICE Trans. Electronics, Vol. E91-C, No. 1, pp. 87-95, Jan. 2008.
18. ``Multi-Path Analog Circuits Robust to Digital Substrate Noise,'' Shigetaka Takagi, Retdian Agung Nicodimus, Kazuyuki Wada, Takahide Sato, and Nobuo Fujii, IEICE Trans. Fundamentals, Vol. E91-A, No. 2, pp. 535-541, Feb. 2008.
19. ``Substrate Noise Cancellation Circuit for Widely Distributed Digital Noise Source,'' Hiroto Suzuki, Kazuyuki Wada, and Yoshiaki Tadokoro, IEICE Trans. Fundamentals, Vol. J92-A, No.4, pp. 216-225, Apr. 2009. (In Japanese)
20. ``Substrate Noise Cancellation Circuit using Cancellation Points,'' Hiroto Suzuki, Kazuyuki Wada, and Yoshiaki Tadokoro, IEEJ Trans. Elect. Inform. and Syst., Vol. 129, No. 8, pp. 1527-1533, Aug. 2009. (In Japanese)
21. ``A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-ƒÊm CMOS,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, IEEE J. Solid-State Circuits, Vol. 44, Issue 10, pp. 2790-2799, Oct. 2009.

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Letters

1. ``Low Voltage CMOS Log-Domain Integrator with DC Gain Improved,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, IEICE Trans. Electronics (Japanese Edition), Vol. J88-C, No. 7, pp. 576-577, July 2005.
2. ``Complex Switched-Capacitor Filter Suppressing Image due to Element Value Mismatches,'' Takeshi Yoshida, Kazuyuki Wada, and Yoshiaki Tadokoro, IEICE Trans. Electronics (Japanese Edition), Vol. J89-C, No. 10, pp. 648-651, Oct. 2006.

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International Conferences (refereed)

1. ``Design Automation for Integrated Continuous-Time Filters using Integrators,'' Kazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, and Nobuo Fujii, Proc. ASPDAC'95, pp. 435-439, Aug. 1995.
2. ``Automatic Tuning System for High-Frequency Integrated Continuous-Time Filters,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISCAS'96, Vol. 1, pp. 85-88, May 1996.
3. ``A Novel Area-Efficient MOSFET-C Filter Design Methodology,'' Shigetaka Takagi, Kazuyuki Wada, Nobuo Fujii, Mohammed Ismail, and Dong Yong Kim, Proc. APCCAS'96, pp. 53-56, Nov. 1996.
4. ``Design of Integrated Continuous-Time Filters with Low Group-Delay Sensitivities,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. APCCAS'96, pp. 65-68, Nov. 1996.
5. ``Reduction of Characteristic Deviations due to Parasitic Elements on Integrator-Based Filters,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISCAS'97, Vol. 1, 345-348, June 1997.
6. ``Reduction in Output DC Offset Voltage of Integrator-Based Filters,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ICECS'98, Vol. 2, pp. 17-20, Sep. 1998.
7. ``Novel Automatic Tuning System using PLL with Switched Capacitor Circuit Technique,'' Shigetaka Takagi, Kazuyuki Wada, Nobuo Fujii, and Takeshi Yanagisawa, Proc. APCCAS'98, pp. 699-702, Nov. 1998.
8. ``Simple Linear Transconductors with Low Power Supply Voltage,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISPACS'99, pp. 629-632, Dec. 1999.
9. ``A Novel Class A CMOS Current Conveyer,'' Sohrab Emami, Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISCAS 2000, Vol. IV, pp. 453-456, May. 2000.
10. ``Power Saving Technique for MOS Differential Amplifiers,'' Kyoichi Takenaka, Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISCAS 2000, Vol. V, pp. 213-216, May. 2000.
11. ``Novel Voltage-Regulating Circuit for Low-Voltage and Low-Power OTA Realization Using MOSFET's in the Non-Saturation Region,'' Takahide Sato, Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISCAS 2000, Vol. V, pp. 477-480, May. 2000.
12. ``Voltage Regulating Circuit Using Depletion-Type MOSFET's and Its Application to Low-Voltage OTA Realization,'' Takahide Sato, Mamoru Nakamura, Shigetaka Takagi, Kazuyuki Wada, and Nobuo Fujii, Proc. 2000 IEEJ International Analog VLSI Workshop, pp. 119-123, June 2000.
13. ``Linear Voltage-to-Current Converter with Wide Dynamic Range,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. 2000 IEEJ International Analog VLSI Workshop, pp. 124-129, June 2000.
14. ``1.5-V OTA Using MOSFET's in Weak-Inversion Region,'' Takahide Sato, Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. ISPACS 2000, pp. 643-646, Nov. 2000.
15. ``Mobility-Reduction-Free Low-Distortion OTA using Backgate-Bias,'' Takahide Sato, Mamoru Nakamura, Shigetaka Takagi, Kazuyuki Wada, and Nobuo Fujii, Proc. APCCAS 2000, pp. 279-282, Dec. 2000.
16. ``Active Guard Band Circuit for Substrate Noise Suppression,'' Shigetaka Takagi, Retdian Agung Nicodimus, Kazuyuki Wada, and Nobuo Fujii, Proc. ISCAS 2001, Vol. I, pp. 548-551, May 2001.
17. ``Preprocessing of Blocking Signal Using a Comparator,'' Kazuyuki Wada, Nobuo Fujii, and Shigetaka Takagi, Proc. 2001 IEEJ International Analog VLSI Workshop, pp. 154-157, May 2001.
18. ``Design of a Body-Effect Reduced-Source Follower and Its Application to Linearization Technique,'' Kazuyuki Wada and Yoshiaki Tadokoro, Proc. ISCAS 2002, Vol. III, pp. 723-726, May 2002.
19. ``RC Polyphase Filter with Flat Gain Characteristic,'' Kazuyuki Wada and Yoshiaki Tadokoro, Proc. ISCAS 2003, Vol. I, pp. 537-540, May 2003.
20. ``Design of Nonlinear Functions of Companding Integrators with Wide Dynamic Ranges,'' Kazuyuki Wada and Yoshiaki Tadokoro, Proc. ECCTD 2003, Vol. I, pp. 213-216, Sep. 2003.
21. ``CMOS Log-Domain Integrator with DC Gain Improved,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro Proc. 2004 IEEJ International Analog VLSI Workshop, pp. 61-66, Oct. 2004.
22. ``Minimization of Total Area in Integrated Active RC Filters,'' Kazuyuki Wada and Randall L. Geiger, Proc. 2006 IEEE International Symposium on Circuits and Systems, May 2006.
23. ``Low-Voltage CMOS Syllabic-Companding Log domain Filter,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 2006 IEEE International Symposium on Circuits and Systems, May 2006.
24. ``Band Connections in Active Cancellation Circuits against Digital Substrate Noise,'' Hiroto Suzuki, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 2006 IEEE International Symposium on Circuits and Systems, May 2006.
25. ``0.8-V CMOS Current Peak Detector and Its Application,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 206 IEEJ Analog VLSI Workshop, Nov. 2006.
26. ``Active Cancellation Circuit using Two Cancellation Points for Digital Substrate Noise Reduction,'' Hiroto Suzuki, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 206 IEEJ Analog VLSI Workshop, Nov. 2006.
27. ``Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 2007 IEEE International Symposium on Circuits and Systems, pp. 2244-2247, May 2007.
28. ``A 1.2-V 18-uW Bias Current Reuse Log Domain Filter for Hearing Aid Application,'' Ippei Akita, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 2007 IEEJ Analog VLSI Workshop, Nov. 2007.
29. ``Substrate Noise Cancellation Tolerant of Large Digital Circuit,'' Hiroto Suzuki, Kazuyuki Wada, and Yoshiaki Tadokoro, Proc. 2008 International Symposium on Communication, Control and Signal Processing, pp. 93-97, Mar. 2008.
30. ``Automatic tuning scheme for substrate noise cancellation circuit tolerant of large digital circuit,'' H. Suzuki, K. Wada, and Y. Tadokoro, Proc. 2008 IEEJ Analog VLSI Workshop, pp.148-152, August 2008.
31. ``Multi-Path Filters Robust to Substrate Noise and Nonlinearity,'' Kazuyuki Wada, Yukiya Kiyokawa, Nicodimus Retdian, Shigetaka Takagi, Takahide Sato, and Nobuo Fujii, Proc. 2009 IEEE International Symposium on Circuits and Systems, pp. 2950-2953, May 2009.

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International Conferences (non-refereed)

1. ``Reduction in Element Value Spreads on Integrator-Based Filters,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. Analog VLSI Workshop '97, pp. 7-12, May 1997.
2. ``Integrator-Based Filter Structures with Good Frequency Characteristics,'' Kazuyuki Wada, Shigetaka Takagi, and Nobuo Fujii, Proc. Analog VLSI Workshop '98, pp. 7-12, May 1998.

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